1. Field of the Invention
This invention relates to a circuit and a method for discharging high voltage nodes to ground.
More particularly this invention relates to a high voltage discharge circuit which prevents semiconductor latch-up and prevents semiconductor damage during the discharge process.
2. Description of Related Art
Integrated circuits typically are made up of electrically alterable memory and flash memory. For the program and erase operations of these writable memories, an internal high voltage is needed. For example, there are high voltages on some internal nodes of flash memories during program and erase operations. These high-voltage nodes have to be carefully discharged to ground after the program or erase operations are completed. These high voltages must be discharged. If they are allowed to persist in the high density integrated circuit chip environment, the devices could latch-up or could be damaged.
The typical prior art circuit for discharging on-chip high voltages consists of a serial connection of N channel metal oxide semiconductor field effect transistors, NMOS FETs. This serial path of NMOS FETs will discharge the high voltage in a timely fashion and without damage to the serial FETs themselves. However, this prior art circuit can only discharge the high voltage down to a voltage of N times the threshold voltage of an NMOS device, Vt. In the example of 4 serially connected NMOS FETs discharging the high voltage, the resultant voltage level would be approximately 4 times 0.6 volts or 2.4 volts.
Similarly, in a prior art discharge circuit which has an NMOS load device connected in series with another NMOS discharge device, the high voltage can be discharged close to ground. However, with only one discharge device, the discharge current must be kept small due to the large high discharge voltage at the drain of the NMOS FET device. If the NMOS load device has a large current and a large discharge voltage, the NMOS FETs can be damaged. Therefore, in this second prior art circuit, the discharge current must be reduced. The reduced discharge current will produce a slow discharge circuit.
U.S. Pat. No. 5,289,025 (Lee) xe2x80x9cIntegrated Circuit Having a Boosted Nodexe2x80x9d describes a circuit to allow connection of a MOS transistor source/drain region to a voltage boosted above the main power supply. Typical uses include clock driver circuits in microprocessors, row lines in dynamic and static memory chips, and substrate bias generators.
U.S. Pat. No. 5,767,729 (Song) xe2x80x9cDistribution Charge Pump for Nonvolatile Memory Devicexe2x80x9d describes a charge pump circuit for a nonvolatile memory, such as an EEPROM. The voltage on an internal node capacitance progressively rises over subsequent clock pulses until the node reaches a boosted voltage level which is higher than the power supply voltage.
U.S. Pat. No. 6,011,409 (Huang et al.) xe2x80x9cInput/Output Buffer Capable of Accepting An Input Logic Signal Higher in Voltage Level Than the System Voltagexe2x80x9d discloses an I/O circuit capable of accepting a voltage exceeding the chip supply.
It is the objective of this invention to provide a circuit and a method for discharging high voltage in a short amount of time from the nodes of circuits especially integrated circuits.
It is further an object of this invention to prevent latch-up or damage of devices and circuits during the careful discharge of the high voltage to ground.
The objects of this invention are achieved by a high voltage discharge circuit which is made up of a series connected group of NMOS Field effect transistors FETs. The connection from the high voltage node to be discharged to ground via a series of four connected NMOS FETs. Inverters are connected from the drains of the NMOS FETs to the gates of the series connected NMOS FETs, which have two gates for each FET device. The input of the inverters are connected to the drains of the four series connected FETs and the output of the inverters is connected to gate #1 of the four dual-gated FETs. The drains of the four series connected FETs are connected to gate #2 of the dual-gated FETs. The drain of the first series connected FET is connected to the highest voltage node. The source of the first series connected FET is connected to the drain of the second series connected FET. The source of the second series connected FET is connected to the drain of the third series connected FET. The source of the third series connected FET is connected to the drain of the fourth series connected FET. The source of the fourth series connected FET is connected to the drain of a bias FET device. The source of the bias FET is connected to ground. The gate of the bias FET is connected to a voltage bias. The bias FET conducts a discharge current to ground.